To its customers SinTau Srl guarantees experience, versatility and ideas to achieve the objectives and optimize the processes through a complete consultation and rapidity of development thanks to the continuous updating in IT.

GSM Box - Gateway PSTN to GSM

Design and implementation of all units of the system
Hw and Sw Design
Involved technologies : SPI, GSM, PCM, Java Midlet, modem, microcontroller,
Cinterion TC-65i, Silabs ProSLIC Si3210

Janus – Voice and Video over IP intercom device

Design and implementation of all units of the system
Hw and Sw Design
Main customer: Campus Biomedico Roma
Involved technologies : TCP/IP, SIP, RS-232, Java, C/C++, Linux
embedded, Samsung S5PC100 processor, RFID, fingerprint and face recognition, OpenCV

CaReMS – POS (Point of Sale) Management System

Software architecture and design, software implementation,
GUI implementation, web configurator implementation
Main customer: Giesse Ristorazione – Gruppo GRECO
Involved technologies: TCP/IP, RS-232, Java, PHP,
JavaPOS libraries, RFID/HID, barcode

eMobility – Communication module for EVSE charging point

Design and implementation of the communication system in PLC technology
HomePlugAV and HomeGrrenPHY..
Hw and Sw design
Main customer: Ducati Energia
Involved technologies: TCP/IP, SPI, C/C++, Linux embedded, XML, standard
ISO15118 V2G

TSwicth – Railway Systems Router/Switch

Design and implementation of all units of the system .
Hw and Sw design
Main customer: FAR Systems Spa
Involved technologies: ORCAD, Mentor Expedition, C/C++

GROPIUS – MultiUtility Concentrator for Smart City and IoT

Design and implementation of all units of the system .
Hw and Sw design
Main customer: SinTau
Involved technologies: ORCAD, Mentor Expedition, C/C++, Zabbix

Shawl – Shared Access system for WAN links with WiFi/3G Offload

Design and implementation of all units of the system .
Hw and Sw design
Main customer: SinTau
Involved technologies: ORCAD, Mentor Expedition, C/C++, Zabbix

FPGA and ASIC designs

E1 (2Mb/s) lines telemanagement system

All the 2 Mb/s termination and management functions have been implemented.


Low order path termination and adaptation (LPT12 and LPA12) functions have been implemented for the assembly and disassembling of tributary channels in a virtual VC12 container. In particular, a pointer processor was implemented. Some PI functions have been developed, such as clock recovery and HDB3 jitter and wander reduction.
A test bench was created that generates the SDH frame, in order to test all the various functionalities.

Contigous to virtual concatenation converter

A bidirectional conversion of contiguous/virtual concatenation has been implemented in SDH
The main functions implemented in the conversion from contiguous (STM-4_4c) to virtual (STM-4_4v) are:
– Frame alignment & byte boundary of STM4
– Deserialization fo data stream
– Descrambler
– SOH processing (B1 check,B2 check, B2 Excessive BER,M1 gen, M2 gen, SOH buffering)
– Contiguous to Virtual Concatenation Conversion
– AU4-4c pointer interpreter
– VC4-4c/VC4-4v Conversion
– POH processing for AU4-4v
– Pointer generation
– STM16 Framer
The main functions implemented in the Virtual (STM-4_4v) to contiguous (STM-4_4c) concatenation are:
– Deserialization fo data stream
– STM16 Frame Alignment
– STM-4 Extraction
– Virtual/Contiguous Concatenation Conversion
– VC4-4v to VC4-4c Conversion
– AU4-4v pointer interpreter
– VC4-4v H4 processing
– Quadri channel SDRAM interface (SDRAMs have been used to store up to 4 x 2048 frames and to compensate the differential delay (max 256 ms) among the 4 different VC4s of the VC4-4v)
– VC4-4v J1 Check
– POH Conversion from VC4-4v to VC4-4c
– AU4-4c Pointer Generation
– SOH Generation
– Scrambler
– Data Serializzation

Management system for DCC,EOW and OH channels

– OHCC (OverHead Cross Connection) functionalities
– Synchronisation Status Message (SSM) processing
– DCC channels cross connection
– Fan control
– EOW channels processing
– Sa bits processing
– 2 Mb/s signal quality extraction by Sa bits

STM64 Framer

All the functionalities of an STM64 SDH Framer
– SDH/GbE internetworking system
The main functions implemented for the SDH-GbE on ATM stack are:
– ATM termination/ ATM framing and trafic shaping algorithm
– IP PDU management
– Ethernet framing /Ethernet termination
– Load balancing alghoritm
– Utopia interface
– ZBT ram interface 3/5
– MAC interface

GFP mapping of Ethernet packets with QoS classification and management

The main functions implemented in the device are:
– MAC interface
– Classifier ethernet packets : The classifier block manages the writing operations of ethernet packets into an external synchronous SRAM(1Mx18)divided into four queues. The following criteria can be used for queue selection:
– VLAN identifier
– IEEE 802.1p (3 bit VLAN priority field, 8 values)
– IPv4 (DSCP, 64 values)
For each of these classifiers the associated queue (0 to 3) is defined; a priority level can be set among the 3 different classification criteria (1, 2 or 3; same priority cannot be assigned twice). When a new ethernet packet arrives, the table corresponding to the higher priority classifier is addressed to identify the queue where the packet has to be stored. In case of invalid read data, the table corresponding to the next higher priority level classifier is addressed.
Scheduler: The scheduler block manages the reading operation from the queues.
For each of the 4 queues (0 to 3) a priority level can be assigned (queue_strict_prio) and a WFQ value is given (queue_weight, 1 to 31). Priority level acts as a strict priority (a higher priority queue is always emptied before serving a lower priority one);
WFQ is only applied within the same priority level: traffic (number of packets) is assigned in proportion to the relative WFQ values of same priority queue.
A WFQ value of N allows the queue to send N packets for each scheduler round.
Mapping GFP Mapping of Ethernet packets in the 2xSTM-1 or 1xSTM-1 radio frame will be performed using a prioprietary framing protocol derived from GFP. Only the frame delineation functions will be taken from GFP in order to reduce the overhead on the Ethernet packets. The Figure 5.10.1 depicts the GFP-like frame.

VLAN concentrato on 10 Gb7s interface

The main functions implemented in this device are:
– MAC interface
– SPI4 interface
– DMAC and VLAN ID fields extraction
– VLAN tables access and e MAC extraction for the associated channel and PA field write
– fifo writing
– Ram reading
– Round Robin implementation
– Back pressure

Clock recovery and data processing system for 2 Mb/s serial lines

In master mode it manages the communication via the high speed serial data line modalità master of the frequency and the speed of the system own reference to other units configured as slave.
In slave mode, it recovers the clock signal from the received serial data and, with the same external conditions, the same phase distance is guaranteed with respect to the master clock signal, either after a restart of one or the other card, or after a possible anomaly on the communication.
The main functions used and developed are:
– PI interface
– DDR2 controller
– Transceivers blocks
– RS232 interface
– FLASH controller

Management and control system of the TAV trains signaling buoys

The main functions used and developed are:
– Implementation of an Application Specific Processor for the communication and management of the commands coming from the processing unit;
– Implementation of all the peripherals defined in the EuroBalise standard (C1, C6, A1, A4, etc)
– Interfacing and management of high speed ADC and DAC converters
– ZBT RAM interface
– Sinusiodal waveforms generationi

Image processing and management system

The main functions used and developed are:
– Reception of a set of images via an RS232 serial connection and appropriate sending to a flash for storage;
– Selection of a subset of images stored in flash, reading and sending, via an SPI serial interface, to the OLED displays for the visualization.
– Use of an internal microprocessor to control the various interfaces through the “Eclipse” environment.

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