QUIPU – Armada370 Networking Computer On Module

QUIPU - Armada370 Networking Computer On Module

A370_Q7_COM is a module concept combining an high perfomance SoC 88F6710 and core logic (SDRAM and Flash) on a small form factor Q7 COM (Computer On Module). The 88F6710 is a complete system-on-chip (SoC) solution based on Marvell Core Processor embedded CPU technology. The 88F6710 integrate a Superscalar processor with ARMv7-compliant Marvell Core Processor that includes Marvell micro-architecture enhancements and a double precision IEEEcompliant Floating Point Unit (FPU), 256KB Layer 2 (L2) cache, low latency and high bandwidth DDR3 memory controller and 4 integrated multi speed SERDES lanes. The advanced IO peripherals for these devices include PCI Express (PCIe) Gen 2.0, USB 2.0 with integrated PHY, SATA II ports, Ethernet, I2S and TDM.

Core Logic

• Marvell 88F6710 CPU [1.2 GHz]

Memory

• 512MB/1GB DDR3-667 SDRAM
• 1GB Nand Flash
• 1MB SPI Flash

USB Ports

• Usb 2.0 compatible
• EHCI Host controller
• As host support dircet connection at all speeds (LS, FS, HS)
• As device, connects to all host and hub types
• Six independent end points
• Dedicated DMA

Network Interface

• 2 SGMII @ 10/100/1000 Mbps
• Support for link aggregation
• Priority Queueing (DA or VLAN Tag)
• Per queue and per port egress rate shaping
• Support for long frame (up to 10 KB)
• TCP/IP and UDP/IP acceleration on transmit and receive
• 802.3az EEE (Energy Efficient Ethernet)

PCI Express Interface

• PCI Express Gen 1.1 at 2.5 Gbps or Gen2.0 at 5 Gbps
• Port may be configured as Root Complex or Endpoint
• Lane polarity inversion support
• Maximum payload size of 128 bytes
• Power management
• Extended PCI Express configuration space
• Error mesaage support

SATA II Interface

• Compliant with SATA II Phase 1 specifications
• Supports SATA II Phase 2 advanced features
• Supports external SATA (eSATA)
• Supports device 48 bit addressing
• EDMA for the SATA port
• Read ahead

I2C Interface

• General purpose I2C master/slave
• EEPROM serial initialization suppo

SPI Interface

• General purpose SPI interface
• 2 Chip Select
• Configurable clock polarity and pahse
• Supports direct access to SPI slave

SD/SDIO Interface

• 1bit/4bitSD/SDIOcards
• SDPHY1,1upto50MHz
• Supports SDHC cards (SD PHY 2.0)
• Hardware generate/check CRC on all command

Uart Interface

• 16750 UART compatible
• Two pins for TX and RX operations without Flow Control

I2S Interface

• Sample rates of 44.1/48/96 KHz
• I2S input and output operate at the same sample rate
• I2S input and output support independent bit depths
• Support plain I2S right justified and left justified formats

SD/SDIO Interface

• 1bit/4bitSD/SDIOcards
• SDPHY1,1upto50MHz
• Supports SDHC cards (SD PHY 2.0)
• Hardware generate/check CRC on all command

TDM Interface

• Support 2 voice channels
• TDM with up to 128 full duplex timeslots
• Support for various bit clock rates (256 Khz to 8.192 KHz)
• Support A-law/U-law, linear or wideband channels

Environment

• 0°… 70°C (operating), commercial
• -25°… 85°C (operating), extended commercial

SD/SDIO Interface

• 1bit/4bitSD/SDIOcards
• SDPHY1,1upto50MHz
• Supports SDHC cards (SD PHY 2.0)
• Hardware generate/check CRC on all command

Power Supply

• +5V DC +/-5%
• +3V6…+4V2 (single Lithium cell)

Software

• U-Boot boot loader
• Linux Operating System BSP